This invention relates to digital logic systems, and particularly to a circuit for regulating the duty cycle of a clock produced by a crystal oscillator.
In the field of digital logic systems, improved design and manufacturing techniques have afforded a substantial increase in the operating speed of clocked integrated circuit devices, such as microprocessors and semiconductor memory chips. For example, state-of-the-art microprocessors have operating speeds which may approach or exceed 50-Mhz; such devices must be "driven" by a clock circuit having a cycle of 20-nSec or less. Furthermore, such devices often have strict requirements as to the type of waveform produced by these oscillators.
One measure of the quality of an oscillator waveform is the ratio of time the clock is at a substantially "high" logical level (on) to the time the clock is at a substantially "low" logical level (off). This ratio is referred to as the "duty cycle" of the clock, and can be quantified as the percentage of time the clock is on over one period of oscillation. Thus, for example, an ideal square wave has a 50% duty cycle, wherein the clock is on for exactly one-half the period of oscillation, and off for the other half.
Since a very high speed crystal oscillator will typically not produce an ideal, square-wave output, clocked semiconductor devices may require that the duty cycle fall at least within a specified tolerance. For example, a semiconductor device manufacturer may specify that the clock for a microprocessor have a guaranteed duty cycle of better than 40% to 60%, thus ensuring that the clock will neither be on nor off for more than 60% of one period or less than 40% of one period.
As the operating speed of logic devices has increased, the requirements for the duty cycle of clock circuits to drive them has correspondingly increased. Manufacturers of devices such as the 80386, 80387 and 82385 microprocessor parts made by Intel are specifying duty cycles of 45% to 55%; other devices such as a Weitek numeric coprocessor specify 47% to 53%. For a device capable of operating at 50-Mhz, however, a 45% to 55% duty cycle requirement imposes a constraint upon the propagation time; the clock must have high-to-low and low-to-high propagation times (the times required for the oscillator to make high-to-low level or low-to-high-level transitions, respectively) less than about 1 nSec (5% of 20-nSec). Moreover, for a 47% to 53% duty cycle specification, the high-to-low and low-to-high propagations of a 50-Mhz clock should be consistently matched to less than 0.6 nSec (3% of 20-nSec). Such strict requirements are met by few, if any, currently available off-the-shelf TTL or CMOS clock devices.
A desktop computer uses a commercially-available crystal oscillator, purchased from manufacturers of such devices, to supply a low-level clock signal of the proper frequency, but this low-level signal must be distributed throughout the board and chassis, and so must be buffered to provide adequate drive. The TTL or CMOS clock buffer circuits needed for this function are not readily constructed using currently available integrated circuit devices.
It is therefore a principle object of this invention to provide an improved high-performance clock voltage source for a computer or the like. Another object is to provide a clock source using commercially-available devices but yet providing tighter tolerances than otherwise permitted using these devices. A further object of the present invention is to provide an apparatus for adapting currently available clock drivers to bring them into conformance with the increasingly rigid standards of operation required in higher-frequency clocked devices.